View AD7694BRMZ_6531425.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

16-bit, 250 ksps pulsar ? adc in msop ad7694 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features 16-bit resolution with no missing codes throughput: 250 ksps @ 5 v inl: 4 lsb max s/(n + d): 92 db @ 20 khz thd: C106 db @ 20 khz pseudo-differential analog input range: 0 v to v ref with v ref up to vdd no pipeline delay single-supply operation: 2.7 v or 5 v serial interface spi?/qspi? /microwire?/dsp-compatible supply current: 540 a @ 2.7 v/100 ksps, 800 a @ 5 v/100 ksps standby current: 1 na 8-lead msop package improved second source to ltc1864 and ltc1864l applications battery-powered equipment data acquisition instrumentation medical instruments process control general description the ad7694 is a 16-bit, charge redistribution, successive approximation, pulsar analog-to-digital converter (adc) that operates from a single power supply, vdd, between 2.7 v to 5.25 v. it contains a low power, high speed, 16-bit sampling adc with no missing codes (b grade), an internal conversion clock, and a serial, spi-compatible interface port. the part also contains a low noise, wide bandwidth, short aperture delay track-and-hold circuit. on the cnv rising edge, it samples an analog input, in+, between 0 v to ref with respect to a ground sense, in?. the reference voltage, ref, is applied externally and can be set up to the supply voltage. its power scales linearly with throughput. the ad7694 is housed in an 8-lead msop package with an operating temperature specified from ?40c to +85c. application diagram ad7694 ref gnd vdd in+ in? sck sdo cnv 3-wire spi interface 1v to vdd 2.5v to 5v 0 to v ref 05003-001 figure 1. table 1. msop, lfcsp (qfn)/sot-23, 16-bit pulsar adc type 100 ksps 250 ksps 500 ksps true differential ad7684 ad7687 ad7688 pseudo ad7683 ad7685 ad7686 differential/unipolar ad7694 unipolar ad7680
ad7694 rev. a | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 application diagram ........................................................................ 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications ....................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 ter mi nolo g y ...................................................................................... 8 typical performance characteristics ............................................. 9 application information ................................................................ 12 circuit information .................................................................... 12 converter operation .................................................................. 12 transfer functions ..................................................................... 12 typical connection diagram ................................................... 13 analog input ............................................................................... 13 driver amplifier choice ........................................................... 13 voltage reference input ............................................................ 14 power supply ............................................................................... 14 supplying the adc from the reference .................................. 14 digital interface .......................................................................... 15 layout .......................................................................................... 15 evaluating the ad7694s performance .................................... 15 outline dimensions ....................................................................... 16 ordering guide .......................................................................... 16 revision history 5/05rev. 0 to rev. a updated format..................................................................universal changes to digital interface section............................................ 14 changes to figure 25...................................................................... 15 changes to evaluating the ad7694s performance section...... 15 7/04revision 0: initial version
ad7694 rev. a | page 3 of 16 specifications vdd = 2.7 v to 5.25 v; v ref = vdd; t a = C40c to +85c, unless otherwise noted. table 2. a grade b grade parameter conditions min typ max min typ max unit resolution 16 16 bits analog input voltage range in+ ? in? 0 v ref 0 v ref v absolute input voltage in+ ?0.1 vdd + 0.1 ?0.1 vdd + 0.1 v in? ?0.1 +0.1 ?0.1 +0.1 v leakage current at 25c acquisition phase 1 1 na input impedance see the analog input section accuracy no missing codes 15 16 bits integral linearity error ?6 +6 ?4 +4 lsb transition noise ref = vdd = 5 v 0.5 0.5 lsb gain error 1 , t min to t max 2 30 2 15 lsb gain error temperature drift 0.3 0.3 ppm/c offset error 1 , t min to t max 0.7 3.5 0.7 3.5 mv offset temperature drift 0.3 0.3 ppm/c power supply sensitivity vdd = 5 v 5% 0.05 0.05 lsb throughput conversion rate vdd = 4.75 v to 5.25 v 0 250 0 250 ksps vdd = 2.7 v to 4.75 v 0 150 0 150 ksps ac accuracy signal-to-noise f in = 20 khz, v ref = 5 v 90 88 92 db 2 f in = 20 khz, v ref = 2.5 v 86 87 db spurious-free dynamic range f in = 20 khz ?100 ?106 db total harmonic distortion f in = 20 khz ?100 ?106 db signal-to-(noise + distortion) f in = 20 khz, v ref = 5 v 89 88 92 db f in = 20 khz, v ref = 2.5 v 86 87 db 1 see the terminology section. these specif ications include full temperature range va riation, but do not include the error contribution from the external reference. 2 all specifications in db refer to a full-scale input, fs. tested with an input signal at 0.5 db below full scale, unless other wise specified.
ad7694 rev. a | page 4 of 16 vdd = 2.7 v to 5.25 v; v ref = vdd; t a = C40c to +85c, unless otherwise noted. table 3. parameter conditions min typ max unit reference voltage range 1 vdd v load current 250 ksps, v in+ ? v in? = v ref /2 = 2.5 v 50 a sampling dynamics ?3 db input bandwidth 9 mhz digital inputs logic levels v il vdd = 4.75 v 0.8 v vdd = 2.7 v 0.45 v v ih vdd = 5.25 v 3.15 v vdd = 3.3 v 1.9 v i il ?1 +1 a i ih ?1 +1 a digital outputs data format serial, 16 bits straight binary pipeline delay conversion results available immediately after completed conversion v ol i sink = +500 a 0.4 v v oh i source = ?500 a vdd ? 0.3 v power supplies vdd specified performance 2.7 5.25 v operating current vdd vdd = 5 v, 100 ksps throughput 0.8 1.2 ma vdd = 2.7 v, 100 ksps throughput 540 960 a standby current 1 , 2 vdd = 5 v, 25 c 1 50 na temperature range specified performance t min to t max ?40 +85 c 1 with all digital inputs forced to vdd or gnd, as required. 2 during acquisition phase.
ad7694 rev. a | page 5 of 16 timing specifications vdd = 4.75 v to 5.25 v; t a = ?40c to +85c, unless otherwise stated. table 4. parameter symbol min typ max unit conversion time: cnv rising edge to data available t conv 3.2 s time between conversions t cyc 4 s sck period t sck 50 ns sck low time t sckl 20 ns sck high time t sckh 20 ns sck falling edge to data remains valid t hsdo 5 ns sck falling edge to data valid delay t dsdo 20 ns cnv low to sdo, d15 msb valid t en 60 ns cnv high to sdo high impedance t dis 60 ns vdd = 2.7 v to 4.75 v; t a = ?40c to +85c, unless otherwise stated. table 5. parameter symbol min typ max unit conversion time: cnv rising edge to data available t conv 4.66 s time between conversions t cyc 6.66 s sck period t sck 125 ns sck low time t sckl 50 ns sck high time t sckh 50 ns sck falling edge to data remains valid t hsdo 5 ns sck falling edge to data valid delay t dsdo 50 ns cnv low to sdo, d15 msb valid t en 120 ns cnv high to sdo high impedance t dis 120 ns
ad7694 rev. a | page 6 of 16 absolute maximum ratings table 6. parameter rating analog inputs in+ 1 , in? 1 gnd ? 0.3 v to vdd + 0.3 v or 130 ma ref gnd ? 0.3 v to vdd + 0.3 v supply voltages vdd to gnd ?0.3 v to +7 v digital inputs to gnd ?0.3 v to vdd + 0.3 v digital outputs to gnd ?0.3 v to vdd + 0.3 v storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance 200c/w (msop-8) jc thermal impedance 44c/w (msop-8) lead temperature range vapor phase (60 sec) 215c infrared (15 sec) 220c 1 see the analog input section. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. 05003-002 500 ai ol 500 ai oh 1.4v to sdo c l 50pf figure 2. load circuit fo r digital interface timing v il v ih v oh v ol v ol v oh t delay t delay 05003-003 figure 3. voltage reference levels for timing
ad7694 rev. a | page 7 of 16 pin configuration and fu nction descriptions 05003-004 ref 1 in+ 2 in? 3 gnd 4 vdd 8 sck 7 sdo 6 cnv 5 ad7694 top view (not to scale) figure 4. 8-lead msop pin configuration table 7. pin function descriptions pin no. mnemonic type 1 function 1 ref ai reference input voltage. the ref range is from 1 v to vdd. it is referred to the gnd pin. this pin should be decoupled closely to the pin with a ceramic capacitor of a few f. 2 in+ ai analog input. it is referred to in in?. the voltage ra nge, that is, the difference between in+ and in?, which is 0 v to v ref . 3 in? ai analog input ground sense. to be connected to the analog ground plane or to a remote sense ground. 4 gnd p power supply ground. 5 cnv di convert input. on its leading edge, it initiates the conversions. it enables the sdo pin when low. 6 sdo do serial data output. the conversion result is output on this pin. it is synchronized to sck. 7 sck di serial data clock input. when cnv is low, th e conversion result is shifted out by this clock. 8 vdd p power supply. 1 ai = analog input; di = digital input; do = digital output; and p = power.
ad7694 rev. a | page 8 of 16 terminology integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full scale to positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1 ? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line (see figure 19 ). differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. offset error the first transition should occur at a level ? lsb above analog ground (38.1 v for the 0 v to 5 v range). the offset error is the deviation of the actual transition from that point. gain error the last transition (from 111...10 to 111...11) should occur for an analog voltage 1 ? lsb below the nominal full scale (4.999886 v for the 0 v to 5 v range). the gain error is the deviation of the actual level of the last transition from the ideal level after the offset has been adjusted out. spurious-free dynamic range (sfdr) the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to s/(n + d) by enob = (s/[n + d] db ? 1.76)/6.02 and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in db. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in db. signal-to-(noise + distortion) ratio (s/[n + d]) s/(n+d) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/(n+d) is expressed in db. aperture delay aperture delay is a measure of the acquisition performance and the time between the rising edge of the cnv input and the time the input signal is held for conversion. transient resp onse the time required for the adc to accurately acquire its input after a full-scale step function is applied.
ad7694 rev. a | page 9 of 16 typical performance characteristics 4 ?4 ?3 ?2 ?1 0 1 2 3 0 32768 16384 49152 65536 05003-005 code inl (lsb) positive inl = +0.68 lsb negative inl = ?1.14 lsb figure 5. integral nonlinearity vs. code 12000 10000 8000 6000 4000 2000 0 24e0 24e1 24e2 24e3 24e4 24e5 24e6 24e7 24e8 05003-006 code in hex counts 001 00 12500 10003 0 108568 vdd = ref = 5v figure 6. histogram of a dc input at the code center 0 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 120 05003-007 frequency (khz) amplitude (db of full scale) 16384 point fft vdd = ref = 5v f s = 250ksps f in = 20.43khz snr = 92.5db thd = ?109.9db sfdr = ?111.0db figure 7. fft plot 2.0 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 0 32768 16384 49152 65536 05003-008 code dnl (lsb) positive dnl = +0.59 lsb negative dnl = ?0.56 lsb figure 8. differential nonlinearity vs. code 8000 7000 6000 5000 4000 3000 2000 1000 0 251b 251c 251d 251e 251f 2520 2521 2522 2523 2524 2525 2526 05003-009 code in hex counts vdd = ref = 2.5v 0027 2808 50 100 28148 65487 2133 32418 figure 9. histogram of a dc input at the code center 0 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10203040506070 05003-010 frequency (khz) amplitude (db of full scale) 16384 point fft vdd = ref = 2.5v f s = 150ksps f in = 20.43khz snr = 88.5db thd = ?102.7db sfdr = ?105.1db figure 10. fft plot
ad7694 rev. a | page 10 of 16 100 95 90 85 80 17 16 15 14 13 2.5 3.0 3.5 4.0 4.5 5.0 05003-011 reference voltage (v) snr, s/[n+d] (db) enob (bits) snr s/[n+d] enob figure 11. snr, s/(n + d), and enob vs. reference voltage 100 95 90 85 80 75 70 0 50 100 150 200 05003-012 frequency (khz) s/[n+d] (db) v ref = 2.5v, ?1db v ref = 5v, ?10db v ref = 5v, ?1db figure 12. s/[n + d] vs. frequency ?80 ?115 ?110 ?105 ?100 ?95 ?90 ?85 0 40 80 120 160 200 05003-013 frequency (khz) thd (db) v ref = 5v, ?1db v ref = 2.5v, ?1db figure 13. thd vs. frequency 1200 1000 800 600 400 200 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 05003-014 supply (v) operating current ( a) f s = 100ksps figure 14. operating current vs. supply 800 900 400 500 600 700 300 200 100 0 ?55 125 105856545255 ?15 ?35 05003-015 temperature ( c) operating current ( a) vdd = 5v, f s = 100ksps vdd = 2.7v, f s = 100ksps figure 15. operating current vs. temperature 1000 0 250 500 750 ?55 ?35 ?15 5 25 45 65 85 105 125 05003-016 temperature ( c) power-down current (na) figure 16. power-down current vs. temperature
ad7694 rev. a | page 11 of 16 6 ?6 ?4 ?2 0 2 4 ?55 125 105856545255 ?15 ?35 05003-017 temperature ( c) offset error, gain error (lsb) offset error gain error figure 17. offset and gain error vs. temperature
ad7694 rev. a | page 12 of 16 application information sw+ msb 16,384c in+ lsb comp control logic switches control busy output code cnv ref gnd in? 4c 2c c c 32,768c sw? msb 16,384c lsb 4c 2c c c 32,768c 05003-018 figure 18. adc simplified schematic circuit information the ad7694 is a low power, single-supply, 16-bit adc using a successive approximation architecture. it is capable of con- verting 250,000 samples per second (250 ksps) and powers down between conversions. when operating at 100 sps, for example, it typically consumes 4 w, ideal for battery-powered applications. the ad7694 provides the user with on-chip, track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple, multiplexed channel applications. the ad7694 is specified from 2.7 v to 5.25 v. it is housed in an 8-lead msop. the ad7694 is an improved second source to ltc1864 and ltc1864l. for even better performance, the ad7685 should be considered. converter operation the ad7694 is a successive approximation adc based on a charge redistribution dac. figure 18 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs. during the acquisition phase, terminals of the array tied to the comparators input are connected to gnd via sw+ and sw?. all independent switches are connected to the analog inputs. thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in? inputs. when the acquisition phase is complete and the cnv input goes high, a conversion phase begins. when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. thus, the differential voltage between the inputs, in+ and in?, captured at the end of the acquisition phase applies to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and ref, the comparator input varies by binary weighted voltage steps (v ref /2, v ref /4 v ref /65536). the control logic toggles these switches, starting with the msb, in order to bring the comparator back into a balanced condition. after the completion of this process, the part returns to the acquisition phase and the control logic generates the adc output code. because the ad7694 has an on-board conversion clock, the serial clock, sck, is not required for the conversion process. transfer functions the ideal transfer function for the ad7694 is shown in figure 19 and table 8 . 000...000 000...001 000...010 111...101 111...110 111...111 adc code (straight binary) analog input +fs ? 1.5 lsb + fs ? 1 lsb ?fs + 1 lsb ?fs ?fs + 0.5 lsb 05003-019 figure 19. adc ideal transfer function table 8. output codes and ideal input voltages description analog input v ref = 5 v digital output code hexadecimal fsr C 1 lsb 4.999924 v ffff 1 midscale + 1 lsb 2.500076 v 8001 midscale 2.5 v 8000 midscale C 1 lsb 2.499924 v 7fff Cfsr + 1 lsb 76.3 v 0001 Cfsr 0 v 0000 2 1 this is also the code for an overranged analog input (v in+ C v inC above v ref C v gnd ). 2 this is also the code for an underranged analog input (v in+ C v inC below v gnd ).
ad7694 rev. a | page 13 of 16 05003-020 ad7694 ref gnd vdd in? in+ sck sdo cnv 3-wire interface 100nf 2.7v to 5.25v 2.2 to 10 f (note 2) ref 0 to v ref 33 2.7nf (note 3) (note 4) (note 1) notes 1. see reference section for reference selection. 2 . c ref is usually a 10 f ceramic capacitor (x5r). 3. see driver amplifier choice section. 4 . optional filter. see analog input section . figure 20. typical application diagram typical connection diagram figure 20 shows an example of the recommended application diagram for the ad7694. analog input figure 21 shows an equivalent circuit of the ad7694 input structure. the two diodes, d1 and d2, provide esd protection for the analog inputs, in+ and in?. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 v, because this will cause these diodes to become forward-biased and start conducting current. however, these diodes can handle a forward-biased current of 130 ma maximum. for instance, these conditions could eventually occur when the input buffers (u1) supplies are different from vdd. in such a case, an input buffer with a short-circuit, current limitation can be used to protect the part. 05003-021 c in r in d1 d2 c pin in+ or in? gnd vdd figure 21. equivalent analog input circuit this analog input structure allows the sampling of the differential signal between in+ and in?. by using this differential input, small signals common to both inputs are rejected. for instance, by using in? to sense a remote signal ground, ground potential differences between the sensor and the local adc ground are eliminated. during the acquisition phase, the impedance of the analog input in+ can be modeled as a parallel combination of the capacitor c pin and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 600 and is a lumped component made up of some serial resistors and the on resistance of the switches. c in is typically 30 pf and is mainly the adc sampling capacitor. during the conversion phase, where the switches are opened, the input impedance is limited to c pin . r in and c in make a 1-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise. when the source impedance of the driving circuit is low, the ad7694 can be driven directly. large source impedances significantly affect the ac performance, especially total harmonic distortion (thd). the dc performances are less sensitive to the input impedance. driver amplifier choice although the ad7694 is easy to drive, the driver amplifier needs to meet the following requirements: ? the noise generated by the driver amplifier needs to be kept as low as possible to preserve the snr and transition noise performance of the ad7694. note that the ad7694 has a noise much lower than most of the other 16-bit adcs and, therefore, can be driven by a noisier op amp while preserving the same or better system perfor- mance. the noise coming from the driver is filtered by the ad7694 analog input circuit 1-pole, low-pass filter made by r1 and c2 or by the external filter, if one is used. ? for ac applications, the driver needs to have a thd performance suitable to that of the ad7694. figure 13 gives the thd vs. frequency that the driver should exceed. ? for multichannel, multiplexed applications, the driver amplifier and the ad7694 analog input circuit must be able to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). in the amplifiers data sheet, settling at 0.1% to 0.01% is more commonly specified. this could differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection.
ad7694 rev. a | page 14 of 16 table 9. recommended driver amplifiers amplifier typical application ad8021 very low noise and high frequency ad8022 low noise and high frequency op184 low power, low noise, and low frequency ad8605 , ad8615 5 v single-supply and low power ad8519 small, low power, and low frequency ad8031 high frequency and low power voltage reference input the ad7694 voltage reference input, ref, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the ref and gnd pins, as explained in the layout section. when ref is driven by a very low impedance source (for example, an unbuffered reference voltage like the low temperature drift adr43x reference or a reference buffer using the ad8031 or the ad8605 ), a 10 f (x5r, 0805 size) ceramic chip capacitor is appropriate for optimum performance. if desired, smaller reference decoupling capacitor values down to 2.2 f can be used with a minimal impact on performance, especially dnl. power supply the ad7694 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate, as shown in figure 22 . this makes the part ideal for a low sampling rate (even a few hz) and low battery- powered applications. 10,000 1,000 100 10 1 0.1 0.01 10 100 1k 10k 100k 1m 05003-022 sampling rate (sps) operating current ( a) vdd = 5v vdd = 2.7v figure 22. operating current vs. sampling rate supplying the adc from the reference for simplified applications, the ad7694, with its low operating current, can be supplied directly using the reference circuit, as shown in figure 23 . the reference line can be driven by either ? the system power supply directly ? a reference voltage with enough current output capability, such as the adr43x ? a reference buffer, such as the ad8031 , that can also filter the system power supply, as shown in figure 23 05003-023 ad8031 ad7694 ref vdd 2.2 to 10 f 1 f 10 10k 5v or 3v 5v or 3v 5v or 3v 1 f (note 1) notes 1. optional reference buffer and filter. figure 23. example of an application circuit
ad7694 rev. a | page 15 of 16 05003-025 sdo 1 sdo remains low if further sck clocks are applied while cnv is low. d15 d14 d13 d1 d0 t dis sck 1 2 3 14 15 16 1 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition t acq t en figure 24. serial interface timing digital interface the ad7694 is compatible with spi, qspi, digital hosts, and dsps, for example, blackfin? adsp-bf53x or adsp-219x. the connection diagram is shown in figure 25 and the corresponding timing diagram is shown in figure 24 . a rising edge on cnv initiates a conversion and forces sdo to high impedance. when the conversion is complete, the ad7694 enters the acquisition phase and powers down. when cnv goes low, the msb is output onto sdo. the remaining data bits are clocked by sck falling edges. the data is valid on both sck edges. 05003-024 cnv sck sdo data in clk convert digital host ad7694 figure 25. connection diagram layout the printed circuit board that houses the ad7694 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the ad7694 with all its analog signals on the left side and all its digital signals on the right side eases this task. avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the ad7694 is used as a shield. fast switching signals, such as cnv or clocks, should never run near analog signal paths. crossover of digital and analog signals should be avoided. at least one ground plane should be used. it could be common or split between the digital and analog section. in such a case, it should be joined underneath the ad7694s. the ad7694 voltage reference input ref has a dynamic input impedance and should be decoupled with minimal parasitic inductances. that is done by placing the reference decoupling ceramic capacitor close to, and ideally right up against, the ref and gnd pins and by connecting these pins with wide, low impedance traces. finally, the power supply, vdd, of the ad7694 should be decoupled with a ceramic capacitor, typically 100 nf. this capacitor should be placed close to the ad7694 and connected using short and large traces to provide low impedance paths and reduce the effect of glitches on the power supply lines. evaluating the ad7694s performance other recommended layouts for the ad7694 are outlined in the evaluation board for the ad7694 ( eval-ad7694 ). the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the eval-control brd3 .
ad7694 rev. a | page 16 of 16 outline dimensions 0.80 0.60 0.40 8 0 4 8 1 5 4.90 bsc pin 1 0.65 bsc 3.00 bsc seating plane 0 .15 0 .00 0.38 0.22 1.10 max 3.00 bsc coplanarity 0.10 0.23 0.08 compliant to jedec standards mo-187-aa figure 26. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters ordering guide model integral nonlinearity temperature range package description package option transport media, quantity branding ad7694arm 6 lsb max C40c to +85c msop rm-8 tube, 50 c2h ad7694armrl7 6 lsb max C40c to +85c msop rm-8 reel, 1,000 c2h ad7694brm 4 lsb max C40c to +85c msop rm-8 tube, 50 c2j ad7694brmrl7 4 lsb max C40c to +85c msop rm-8 reel, 1,000 c2j eval-ad7694cb 1 evaluation board eval-control brd2 2 controller board eval-control brd3 2 controller board 1 this board can be used as a standalone evaluation board or in conjunction with the eval-control brdx for evaluation/demonstrat ion purposes. 2 these boards allow a pc to control and communicate with all analog devices evaluation boards ending in cb designators. ?2005 analog devices, inc. all ri ghts reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05003C0C5/05(a)

▲Up To Search▲

Price & Availability of AD7694BRMZ

	To Download AD7694BRMZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .